Reduction of Interface State Density in 4H-SiC MOS Capacitors Modified by ALD-Deposited Interlayers

Zhenyu Wang; Zhaopeng Bai; Yunduo Guo; Chengxi Ding; Qimin Huang; Lin Gu; Yi Shen; Qingchun Zhang; Hongping Ma

doi:10.3390/nano15070555

Reduction of Interface State Density in 4H-SiC MOS Capacitors Modified by ALD-Deposited Interlayers

Nanomaterials (Basel). 2025 Apr 5;15(7):555. doi: 10.3390/nano15070555.

Authors

Zhenyu Wang^{1

2}, Zhaopeng Bai^{1

2}, Yunduo Guo^{1

2}, Chengxi Ding^{1

2}, Qimin Huang^{1

2}, Lin Gu^{1

2}, Yi Shen^{1

2}, Qingchun Zhang^{1

2

3}, Hongping Ma^{1

2

3}

Affiliations

¹ Institute of Wide Bandgap Semiconductors and Future Lighting, Academy for Engineering & Technology, Fudan University, Shanghai 200433, China.
² Shanghai Research Center for Silicon Carbide Power Devices Engineering & Technology, Fudan University, Shanghai 200433, China.
³ Institute of Wide Bandgap Semiconductor Materials and Devices, Research Institute of Fudan University in Ningbo, Ningbo 315327, China.

Abstract

This study proposed an innovative method for growing gate oxide on silicon carbide (SiC), where silicon oxide (SiO₂) was fabricated on a deposited Al₂O₃ layer, achieving high quality gate oxide. A thin Al₂O₃ passivation layer was deposited via atomic layer deposition (ALD), followed by Si deposition and reoxidation to fabricate a MOS structure. The effects of different ALD growth cycles on the interface chemical composition, trap density, breakdown characteristics, and bias stress stability of the MOS capacitors were systematically investigated. X-ray photoelectron spectroscopy (XPS) analyses revealed that an ALD Al₂O₃ passivation layer with 10 growth cycles effectively suppresses the formation of the proportion of Si-O_xC_y bonds. Additionally, the SiO₂/Al₂O₃/SiC gate stack with 10 ALD growth cycles exhibited optimal electrical properties, including a minimum interface state density (D_it) value of 3 × 10¹¹ cm^-2 eV^-1 and a breakdown field (E_bd) of 10.9 MV/cm. We also systematically analyzed the bias stress stability of the capacitors at room temperature and elevated temperatures. Analysis of flat-band voltage (ΔV_fb) and midgap voltage (ΔV_mg) hysteresis after high-temperature positive and negative bias stress demonstrated that incorporating a thin Al₂O₃ layer at the interface is the key factor in enhancing the stability of V_fb and midgap voltage V_mg.

Keywords: 4H-SiC; SiC/SiO2 interfaces; capacitors; electrical properties.

Abstract

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