The development of semiconductor processes and advanced packaging technology has promoted significant advancements in the miniaturization and integration of electronic devices and systems. However, these developments present substantial challenges to the thermal and stress design of current chips, necessitating novel approaches to address these issues. Traditional finite element simulation-assisted design methods have proven inadequate in meeting the demands of highly integrated electronic devices and microsystems due to their inability to effectively simulate the integration process, cross-scale, and multi-physical field coupling. To address these challenges and shorten the design and development period of electronic devices and microsystems, rigorous thermal and stress testing and analyses must be conducted. A promising approach is the utilization of TTC (thermal test chip) technology, a novel in situ testing method, as the primary tool for thermal/stress testing and analyses of the internal interfaces of electronic devices and microsystems. This technology has emerged as a crucial element in validating thermal/stress processes during packaging, as well as in the design of effective heat dissipation solutions. This paper is structured as follows: first, it introduces the principle of thermal test chips; second, it summarizes the domestic and international research progress and index parameter comparison of thermal test chips, as well as the application progress in chip packaging and heat dissipation; and finally, it looks forward to the application prospect of thermal test chips in microsystem design and advanced packaging.
Keywords: JESD51-4; microsystem; thermal test chip; thermal/stress test.