Matching constraints in an analog integrated circuit (IC) are critical to optimizing layout performance. To extract these matching constraints accurately and efficiently from the netlist, we propose the heterogeneous matching constraint extraction graph neural network (MCE-HGCN). First, the netlist is mapped into a heterogeneous attribute multi-graph, and based on the characteristics of analog IC matching constraints, a mixed-domain attention mechanism is developed to leverage both the topology information and node attributes in the graph to characterize node embeddings. A matching classifier, implemented using the support vector machine (SVM), is then employed to classify different types of matching constraints from the netlist. Additionally, a matching filter is introduced to remove interference terms. Experimental results demonstrate that the MCE-HGCN model converges effectively with small datasets. In the matching prediction process, the mean F1 score reached 0.917 across different netlist processes and circuit types while maintaining a shorter runtime compared to other methods. Ablation experiments also show that incorporating the mixed-domain attention mechanism and the matching filter individually leads to significant performance improvements. Overall, MCE-HGCN excels at extracting matching constraints from various analog circuits and processes, offering valuable insights for placement guidance and enhancing the efficiency of analog IC layout design.
Keywords: analog IC; heterogeneous multi-graph; matching constraints; mixed attentions; small dataset.